1. Field of the Invention
This invention relates to memory subsystems and more particularly to the use of parity error checking in computer systems utilizing dynamic memory. The invention also relates to a system for automatically enabling or disabling parity generation depending upon whether a particular memory bank supports parity.
2. Description of the Relevant Art
Many computer systems today allow a user to enable or disable system parity generation via software command based upon the type of dynamic memory (DRAM) installed within the system. A problem is that users can purchase two types of DRAM for their computers: one that supports parity error detection and one that does not. The user must first know whether their DRAM supports parity error checking and, if so, they must also know how to properly configure their system to take advantage of this feature. In addition, all DRAM banks in the system must support parity error checking in order for the system parity error checking to work properly, and thus if one bank cannot support parity, the parity capabilities of the other banks go unused.
Parity is the simplest form of error detection. Parity of a digital byte (for example, of 8 bits) can be either even or odd and is determined by the number of ones the word contains. For each 8-bit byte a ninth bit, or parity bit, is appended to the byte. For odd parity, the parity bit will be set to one if there is an even number of ones in the byte, and the parity bit will be set to zero if there is an odd number of ones in the byte. A parity error is detected upon reading the data byte and verifying the parity of that word. When the data word is read, a new parity bit is generated and compared with the original parity bit. If the two do not match, an error has occurred.
Parity is an error detecting mechanism; it cannot be used to correct an error since it is not known in which bit the error occurred. Therefore, when a parity error occurs there is not much that can be done except to halt the system and/or alert the user. Normally this function is done by asserting the microprocessor's halt, wait, or non-maskable interrupt (NMI). While it may be desirable to automatically reset the system, most systems display a warning and prompt the user to restart the system. The effect of a user disabling parity error checking in a computer system is that the NMI generation function due to a parity error is disabled. Therefore, if an error occurs due to incorrect parity (because the DRAM does not support parity), the system will not generate an NMI and the system will not halt.
As stated previously, to properly configure a computer system, the user must first be aware of whether his or her DRAM supports parity error checking. This is not necessarily a simple task. Component failures, especially memory chips, are common occurrences in today's computer systems. Memory systems consisting of a 4-Mbyte array of 256K DRAM chips can have a mean time between failures of less than 9 months. Both types of DRAM may be used as replacements for the failed chip, which can cause confusion as to the type of DRAM currently found in a machine. Also, when purchasing replacement DRAM chips, the user may be driven by cost concerns and select the cheaper DRAM type which may not support parity error checking. Secondly, a user must know how to enable or disable parity error detection on their computer system. Typically this function can be performed in the setup of the computer system. However, this setup utility is usually only made available to the user upon the user's request. Therefore, if a user has DRAM that supports parity error detection, but the user does not enable this feature in the system, the value of the parity error detection is lost. Lastly, a system will not support parity error checking if the user replaces a memory bank that supported parity with one that does not, thereby rendering the parity checking feature of any other banks useless.